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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appear in this document. contact generalplus technology inc. to obtain the latest version of devi ce specifications before plac ing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. g g 16-bit sound controller with 24k x 16 rom oct. 04, 2013 version 1.3 p p c c e e 0 0 4 4 8 8 a a in addition, generalplus products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the expre ss written approval of generalplus.
GPCE048A ? generalplus technology inc. proprietary & confidential 2 oct. 04, 2013 version: 1.3 table of contents page 1. ? general description .......................................................................................................................................................................... 3 ? 2. ? block diagram ...................................................................................................................................................................................... 3 ? 3. ? features .................................................................................................................................................................................................. 3 ? 4. ? application field .................................................................................................................................................................................. 3 ? 5. ? signal descriptions ............................................................................................................................................................................ 4 ? 5.1. ? pad a ssignment ................................................................................................................................................................................. 5 ? 5.2. ? pin m ap ............................................................................................................................................................................................... 6 ? 6. ? functional descriptions.................................................................................................................................................................. 7 ? 6.1. ? cpu ..................................................................................................................................................................................................... 7 ? 6.2. ? m emory ............................................................................................................................................................................................... 7 ? 6.3. ? pll, c lock , p ower m ode ................................................................................................................................................................... 7 ? 6.4. ? s tandby m ode ..................................................................................................................................................................................... 7 ? 6.5. ? l ow v oltage d etection and l ow v oltage r eset ............................................................................................................................. 8 ? 6.6. ? i nterrupt ............................................................................................................................................................................................ 8 ? 6.7. ? i/o ........................................................................................................................................................................................................ 8 ? 6.8. ? s pecial f unction in p ort ................................................................................................................................................................... 9 ? 6.9. ? t imer / c ounter ................................................................................................................................................................................ 10 ? 6.10. ? s leep m ode , w akeup , h alt m ode , and w atchdog ...........................................................................................................................11 ? 6.11. ? s oft r eset p rotection ................................................................................................................................................................... 12 ? 6.12. ? adc (a nalog to d igital c onverter ) / dac .................................................................................................................................... 12 ? 6.13. ? spi ..................................................................................................................................................................................................... 12 ? 6.14. ? a udio a lgorithm ............................................................................................................................................................................... 12 ? 7. ? electrical specifications ............................................................................................................................................................. 13 ? 7.1. ? a bsolute m aximum r atings ............................................................................................................................................................. 13 ? 7.2. ? dc c haracteristics (vdd_reg = 3.3v, vddio = 4.5v (p ort a & b), t a = 25 ) ............................................................................ 13 ? 7.3. ? dc c haracteristics (vdd_reg = 3.3v, vddio = 3.3v (p ort a & b), t a = 25 ) ............................................................................ 13 ? 7.4. ? adc c haracteristics (avdd = 3.3v, t a = 25 ) .............................................................................................................................. 1 4 ? 7.5. ? dac c haracteristics (avdd = 3.3v, t a = 25 ) .............................................................................................................................. 1 4 ? 7.6. ? r egulator c haracteristics ( t a = 25 ) ........................................................................................................................................ 15 ? 7.7. ? p ull h igh r esister and vddio ........................................................................................................................................................ 15 ? 7.8. ? p ull l ow r esister and vddio(n ormal pad) ................................................................................................................................. 15 ? 7.9. ? p ull l ow r esister and vddio(iob[7:0] pad with input high ) ....................................................................................................... 15 ? 7.10. ? i/o o utput h igh c urrent i oh and vddio ........................................................................................................................................ 15 ? 7.11. ? i/o o utput l ow c urrent i ol and vddio(n ormal p ad ) ................................................................................................................... 16 ? 7.12. ? i/o o utput l ow c urrent i ol and vddio(h igh driving pad ) ............................................................................................................ 16 ? 7.13. ? dac o utput c urrent iol and avdd ............................................................................................................................................... 16 ? 8. ? application circuits ......................................................................................................................................................................... 17 ? 8.1. ? a pplication c ircuit -(1) ..................................................................................................................................................................... 17 ? 8.2. ? a pplication c ircuit -(2) ..................................................................................................................................................................... 19 ? 8.3. ? a pplication c ircuit -(3) ..................................................................................................................................................................... 21 ? 9. ? package/pad locations ................................................................................................................................................................... 23 ? 9.1. ? o rdering i nformation ..................................................................................................................................................................... 23 ? 9.2. ? p ackage i nformation ....................................................................................................................................................................... 23 ? 10. ? disclaimer ............................................................................................................................................................................................. 24 ? 11. ? revision history ................................................................................................................................................................................. 25 ?
GPCE048A ? generalplus technology inc. proprietary & confidential 3 oct. 04, 2013 version: 1.3 16-bit sound controller with 24k x 16 rom 1. general description GPCE048A, a 16-bit architecture sound controller, features the newest 16-bit microprocessor, ?nsp? (pronounced as micro-n-sp ), developed by sunplus technology. this high processing speed assures the ?nsp? is capable of handling complex digital signal processes eas ily and rapidly. therefore, the GPCE048A is applicable to th e areas of digital sound process and voice recognition. the operating voltage of 2.4v through 5.5v and speed of 0.16mhz through 49.152mhz yield the GPCE048A to be easily used in varieties of applications. the memory capacity includes 24k-word rom plus a 2k-word working sram. other features include 32 programmable multi-functional i/os, three 16-bit timers/counters, 32768hz real time clock, low voltage reset/detection, eight channels 12-bit adc (one channel built-in mic amplifier with auto gain controller), 14-bit dac output and many others. 2. block diagram un'sp 16-bits cpu ad converter mic 16-bits counter/timer / interrupt general i / o port 2k(word) working sram pll / system clock / reset function memory mapping & control x32i x32o ioa[15:0] iob[15:0] micip micin resetb 24k word / gpio special function timebase/watchdog / pwm output fast-speed rom spi mico opi agc v_mic vadref dac dac regulator 3. features ? 16-bit ?nsp? microprocessor ? cpu clock: 0.16mhz - 49.152mhz ? operating voltage: 2.4v - 5.5v ? power regulator build-in with input voltage: 2.4~5.5v, output voltage: 2.4~3.3v ? mask rom operating voltage: 2.4v - 3.6v ? io porta & b operating voltage: 2.4v - 5.5v ? 24k-word fast speed rom ? 2k-word working sram ? software-based audio processing ? standby mode for power saving ? three 16-bit timers/counters ? one 14-bit dac output ? 32 general i/os (bit programmable) ? key wakeup function (ioa0 - 15) ? pll feature for system clock ? 32768hz real time clock (rtc) ? eight channels 12-bit ad converter ? adc external top reference voltage ? built-in microphone amplifier and agc function ? low voltage reset and low voltage detection ? watchdog enable (option) ? one spi serial interface i/o 4. application field ? voice recognition products ? intelligent interactive talking toys ? advanced educational toys ? kids learning products ? kids storybook ? general speech synthesizer ? long duration audio products ? recording / playback products
GPCE048A ? generalplus technology inc. proprietary & confidential 4 oct. 04, 2013 version: 1.3 5. signal descriptions mnemonic pin no. lqfp 64 pin no. type description port a, port b ioa[15:0] 26-35, 38-43 28-37, 40-45 i/o ioa[ 15:0]: bi-directional i/o ports it can be programmed as wakeup i/o pins iob [15:0] 4-1, 56-53, 14-11, 8-5 6-3, 64-61, 16-13, 10-7 i/o iob [15:0]: bi-directional i/o ports power & gnd vddioa 36 38 p power vdd for port a vssioa 37 39 g power gnd for port a vddiob 9 11 p power vdd for port b vssiob 10 12 g power gnd for port b avdd 23 25 p power vdd for ad,da + pll(3.3v) avss 21 23 g power gnd for ad,da + pll vdd 50 54 p power vdd for core (3.3v) vss 49 53 g power gnd for core clk system/ ice interface x32i 48 52 i 32k oscillator crystal input x32o 47 51 o 32k oscillator crystal output option test 51 58 i test mode selection pin, high is test mode and low is normal mode (pad internal pull low) dac dac 24 26 o audio dac output adc micp 19 21 i mic amplifier input positive (internal floating) micn 18 20 i mic amplifier input negative (refer to application circuit) micout 17 19 o mic amplifier output (refer to application circuit) opi 16 18 i audio amplifier negative i nput (refer to application circuit) agc 15 17 io agc by pass filter (refer to application circuit) vmic 22 24 o microphone power supply vadref 20 22 o avref_da reference pin pll vcoin 25 27 i pll low pass filter input other signal resetb 52 59 i system reset pin (active low) (internal 47kohm pull high resistor) vdd_reg 45 47 i positive supply for regulator(2.4v~5.5v) vss_reg 44 46 i ground reference for regulator vdd33_reg 46 48 i/o 3v power output from regulator total: 56 pads
GPCE048A ? generalplus technology inc. proprietary & confidential 5 oct. 04, 2013 version: 1.3 5.1. pad assignment iob[12] iob[13] iob[14] iob[15] iob[0] iob[1] iob[2] iob[3] vddiob vssiob iob[4] iob[5] iob[6] iob[7] ioa[10] ioa[9] ioa[8] ioa[7] ioa[6] vddioa vssioa ioa[5] ioa[4] ioa[3] ioa[2] ioa[1] ioa[0] vdd33_reg vdd_reg vss_reg
GPCE048A ? generalplus technology inc. proprietary & confidential 6 oct. 04, 2013 version: 1.3 5.2. pin map lqfp64 64 iob[13] iob[14] iob[15] iob[0] iob[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc nc iob[12] iob[2] iob[3] vddiob vssiob iob[4] iob[5] iob[6] iob[7] agc 19 20 21 22 23 24 25 26 27 28 29 30 31 opi micout micn micp vadref avss vmic avdd dac vcoin ioa[15] ioa[14] ioa[13] ioa[12] ioa[1] ioa[2] ioa[3] ioa[4] ioa[5] vdd_reg vss_reg ioa[0] vssioa vddioa ioa[6] ioa[7] ioa[8] ioa[9] ioa[10] ioa[11] 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 59 58 57 55 54 53 52 51 50 49 48 nc resetb test nc nc nc vdd vss x32i x32o nc nc vdd33_reg 61 62 63 iob[8] iob[9] iob[10] iob[11] 18 56 60 GPCE048A
GPCE048A ? generalplus technology inc. proprietary & confidential 7 oct. 04, 2013 version: 1.3 6. functional descriptions 6.1. cpu the GPCE048A is equipped with a 16-bit ?nsp?, the newest 16-bit microprocessor by sunplus (pronounced as micro-n-sp). eight registers are involved in ?nsp?: r1 - r4 (general- purpose registers), pc (program counter), sp (stack pointer), base pointer (bp) and sr (segment register). the interrupts include three fiqs (fast interrupt request) and eight irqs (interrupt request), plus one software-interrupt, break. 6.2. memory 6.2.1. sram the amount of sram is 2k-word (including stack), ranged from $0000 through $07ff with access speed of two cpu clock cycles. fosc/n n:1,2,4,8,16,32,64 b2 b1 b0 of p_systemclock(w)($2030h) cpu clock frequency selection cpu clock 32768hz x'tal b7,b6,b5 of p_systemclock(w)($2030h) system clock frequency selection (default : fosc/8) phase lock loop (pll) system clock generator pll out fosc b7 b6 b5 24.576mhz(default) 20.48mhz 32.768mhz 40.96mhz 49.152mhz 6.2.2. rom GPCE048A features a 24k-word high-speed memory with access speed of two cpu clock cycles. 6.3. pll, clock, power mode 6.3.1. pll (phase lock loop) the purpose of pll is to provide a base frequency (32768hz) and to pump the frequency from 20.48mhz to 49.152mhz for system clock (f osc ). the default pll frequency is 24.576mhz. 6.3.1.1. system clock basically, the system clock is provided by pll and programmed by the port_systemclock (w) to determine the clock frequency for system. the default system clock f osc = 24.576mhz and cpu clock is f osc /8 if not specified. the initial cpu clock is fosc/8 after system wakes up and adjusts to desired cpu clock via programming the port_systemc lock (w). this avoids rom reading failure when system awakens. 6.3.1.2. 32768hz rtc the real time clock (rtc) is normally used in watch, clock or other time related products. a 2hz-rtc (0.5 seconds) function is loaded in GPCE048A. the rtc counts the time as well as to wake cpu up whenever rtc occurs. since the rtc is generated each 0.5 seconds, time can be traced by the number of rtc occurrences. in addition, GPCE048A supports 32768hz oscillator in normal mode and auto-power-saving mode. in normal mode, 32768hz osc always runs at the highest power consumption. in auto-power-saving mode, however, it runs at normal mode for the first 7.5 seconds and switches back to power-saving mode automatically to save powers. 6.4. standby mode the GPCE048A features a power savings mode (or called standby mode) for low power applications. to enter standby mode, the desired key wakeup port (ioa[15:0]) must be configured to input first. and read the port_ioa_data to latch the ioa state before entering the standby mode. also remember to enable the corresponding interrupt source(s) for wakeup. after that, stop the cpu clock by writing $5555 into port_system_sleep(w) to enter standby mode. in such mode, sram and i/os remain in the previous states until cpu being awakened. the wakeup sources in GPCE048A include key wake up (ioa[15:0]), rtc wakeup, and irq1 - irq7. after GPCE048A is awakened, cpu will continue to execute the program from the location it slept. programmer can also enable or disable the 32768hz rtc when cpu is in standby mode.
GPCE048A ? generalplus technology inc. proprietary & confidential 8 oct. 04, 2013 version: 1.3 6.5. low voltage detection and low voltage reset 6.5.1. low voltage detection (lvd) the low voltage detection (lvd) reports the circumstance of present voltage. there are four lvd levels to be selected: 2.6v, 2.8v, 3.0v and 3.2v. those levels can be programmed via p_lvd_ctrl. as an example, s uppose lvd is given to 2.8v. when the voltage drops below 2.8v, the b12 of p_lvd_ctrl is read as high. in such state, program can be designed to react this condition. 6.5.2. low voltage reset in addition to the lvd, the GPCE048A has another important function, low voltage reset (lvr). with the lvr function, a reset signal is generated to reset system when the operating voltage drops below lvr level. without lvr, the cpu becomes unstable and malfunctions when the operating voltage drops below lvr level. the lvr will reset all functions to the initial operational (stable) states when the voltage drops below lvr level. 6.6. interrupt the GPCE048A has 13 interrupt sources, grouped into two types, fiq (fast interrupt request) and irq (interrupt request). the priority of fiq is higher than ir q. fiq is the high-priority interrupt while irq is the low-priority one. an irq can be interrupted by a fiq, but not by another irq. a fiq cannot be interrupted by any other interrupt sources. interrupt source interrupt name / fiq name irq priority timer a irq0_tma/fiq_tma 1(high) timer b irq1_tmb/fiq_tmb 2 timer c irq2_tmc/fiq_tmc 3 spi irq3_spi/fiq_spi 4 key wakeup irq5_key/fiq_key 5 ext1 irq5_ext1/fiq_ext1 6 ext2 irq5_ext2/fiq_ext2 7 interrupt source interrupt name / fiq name irq priority 4096hz irq6_4khz/fiq_4khz 8 2048hz irq6_2khz/fiq_2khz 9 512hz irq6_512hz/fiq_512hz 10 64hz irq7_64hz/fiq_64hz 11 16hz irq7_16hz_fiq_16hz 12 2hz irq7_2hz/fiq_2hz 13(low) 6.7. i/o two i/o ports are built in GPCE048A - porta and portb, total has 32 bit-programmable i/os. the porta is a general purpose i/o with programmable wakeup capability, i.e. ioa [15:0] is the key wakeup port. to activate key wakeup function, latch data on port_ioa_data and enable the key wakeup function. wakeup is triggered when the porta state is different from at the time latched. furthermore, the i/o ports can be operated at 5v level, higher than the cpu core which is a 3v level system. suppose system operating voltage is running at 3.3v, then vddio (power for i/o) operates from 3.3v to 5.5v. in such condition, the i/o pad is capable of operating from 0v through vddio. the following diagram is an i/o schematic. although data can be written into the same register through port_data and port_buffer, they can be read from different places, buffer (r) and data (r). register control logic pull high pull low pin pad buffer(r) data(r) port_data(w) port_buffer(w) port_dir(r/w) port_attr(r/w) in addition to a general purpose i/o port function, porta/b also shares/carries some special f unctions. a summary of porta/b special functions is listed as follows:
GPCE048A ? generalplus technology inc. proprietary & confidential 9 oct. 04, 2013 version: 1.3 6.8. special function in port port special function function description note ioa0 io_pwm io_pwm output refer to timer section ioa1 irout ir output - ioa2 - - - ioa3 - - - ioa4 high driving i/o - - ioa5 high driving i/o - - ioa6 high driving i/o - - ioa7 high driving i/o - - feedback input1 - refer to below example 1 ioa8 ext1 external interrupt source 1 (negative edge triggered) set ioa8 as floating input mode ioa9 feedback output1 work with ioa8 by adding a rc circuit between them to get an osc to ext1 interrupt set ioa9 as inverted output feedback input2 - refer to below example 1 ioa10 ext2 external interrupt source 2 (negative edge triggered) set ioa10 as floating input mode ioa11 feedback output2 work with ioa10 by adding a rc circuit between them to get an osc to ext2 interrupts set ioa11 as inverted output ioa12 spi cs spi chip select refer to spi section ioa13 spi ck spi clock refer to spi section ioa14 spi tx spi data output refer to spi section ioa15 spi rx spi data input refer to spi section iob0 an0 adc channel 0 refer to adc section iob1 an1 adc channel 1 refer to adc section iob2 an2 adc channel 2 refer to adc section iob3 an3 adc channel 3 refer to adc section iob4 an4 adc channel 4 refer to adc section iob5 an5 adc channel 5 refer to adc section iob6 an6 adc channel 6 refer to adc section iob7 an7 adc channel 7 refer to adc section
GPCE048A ? generalplus technology inc. proprietary & confidential 10 oct. 04, 2013 version: 1.3 p_timer_ctrl 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 b3 b2 b1 b0 clock source 1 (input 1) 0 1 f rtc f pll f pll f pll f pll f pll f rtc f rtc f rtc f rtc ext2 ext2 ext2 ext2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 b3 b2 b1 b0 clock source 2 (input 2) 0 1 2hz 16hz 64hz ext2 16-bit timer/counter 16-bit pre-load register p_timera_data p_timera_cntr timer a timerout int to interrupt module auto reload ext2 1 2hz 16hz 64hz 1 2hz 16hz 64hz 1 refer to the above table, the configuration of ioa9, ioa10, ioa11, and ioa12 involves feedback function in which an osc frequency can be obtained from ext1 (ext2) by simply adding a rc circuit between ioa8 (ioa10) and ioa9 (ioa11). 6.9. timer / counter GPCE048A provides three 16-bit timers/counters - timera, timerb and timerc or so called universal counters. the clock source of timer a/b/c are from clock source input 1 and clock source input 2 (see below table) which perform and operation to form the varieties of combinations. when timer overflows, a timeout signal (taout) is sent to cpu interrupt module to generate a timer interrupt signal. in addition, timer a/b/c hardware interrupt events can be used to latch the dac audio output and trigger adc conversion. example to timer a, sending a write signal into tma_cnt, the value of tma_data (value=n) will reload into tma_cnt and set an appropriated clock source. timer wills up-count from n, n+1, n+2? 0xffff. an int signal is generated at the moment of timer rolling over from ?0xffff? to ?0x0000?, and an int signal is processed by int controller immediately. at the same time, n will be reloaded into tma_cnt and start counting again. in timer a, the clock input 1 is a high frequency source and clock input 2 is a low frequency clock source. the combination of clock input 1 and 2 provides varieties of speeds to timera/countera - ?1? representing pass signal (not gating), and ?0? meaning timer deactivated. for instance, if input 1=?1?, the clock is depending on input 2. if input 1=?0?, the timera is deactivated. the ext1/etx2 is the external clock source 1 and external clock source 2.
GPCE048A ? generalplus technology inc. proprietary & confidential 11 oct. 04, 2013 version: 1.3 tmxsel input 1 input 2 0000 ?0? ?0? 0001 ?1? ?1? 0010 f rtc ext2 0011 f pll ext2 0100 ext2 64hz 0101 ext2 16hz 0110 ext2 2hz 0111 ext2 ?1? 1000 f rtc 64hz 1001 f rtc 16hz 1010 f rtc 2hz 1011 f rtc ?1? 1100 f pll 64hz 1101 f pll 16hz 1110 f pll 2hz 1111 f pll ?1? the following clock source a/b/c means clock source for timer a/b/c respectively. generally sp eaking, the clock source a and c are fast clock sources and sour ce b comes from rtc system (32768hz). therefore, clock s ource b can be utilized as a precise counter for time counting, e.g., the 2hz clock can be used for real time counting. 6.9.1. io pwm one io pwm which duty is selected from 1/16 to 14/16. example the below figure is a 3/16-duration cycle. the pwmo waveform is made by selecting a pulse width through port_pwm_ctrl. as a result, each 16 cycles will generate a pulse width defined in control port. these pwm signals can be applied for controlling the speed of motor or other devices. tpwmo tduty pwmo timera_timeout 6.9.2. timebase timebase, generated by 32768hz crystal oscillator, is a combination of frequency selection. furthermore, timebase generates 4khz, 2khz, 512hz, 64hz, 16hz and 2hz interrupt sources (fiq6/irq6, fiq7/irq7) for real-time-clock 6.10. sleep mode, wakeup, halt mode, and watchdog 6.10.1. sleep and wakeup modes 1) sleep: after power-on reset, ic starts running until a sleep command is issued. when a sleep command is accepted, ic will turn the system clock (pll) off. after all, it enters sleep mode. 2) wakeup: cpu awaking from sleep mode requires a wakeup signal to turn the system clock (pll) on. the fiq/irq signal makes cpu to complete the wakeup process and initialization. the cpu wakeup source is given in the following table. wakeup source fiq source timer a interrupt timer b interrupt timer c interrupt spi interrupt ext1/ext2/key rtc 6.10.2. watchdog reset the GPCE048A provides another important feature, watchdog reset. if the watchdog function is enabled, a reset signal is generated to reset system when watchdog counter is overflow. the purpose of watchdog is to monitor whether the system operates normally. within a certain period, watchdog register must be cleared. if it is not cleared, cpu assumes the program has been running in an abnormal condition. as a result, the cpu will reset the system to the initial state and start running the program all over again.
GPCE048A ? generalplus technology inc. proprietary & confidential 12 oct. 04, 2013 version: 1.3 6.11. soft reset protection software reset. writes $5555 into p_system_reset will reset the whole system like hardware reset (pull low resetb pin), except a flag will set on in p_system_lvd_ctrl(r/w). 6.12. adc (analog to digital converter) / dac the GPCE048A has eight channels 12-bit adc (analog to digital converter). the function of an adc is to convert analog signal to digital signal, e.g. a voltage level into a digital word. the eight channels of adc can be seven channels of line-in from iob [7:0] or one channel microphone (mic) input through amplifier and agc controller. the mic amplifie r circuit is capable of reducing common mode noise by transmitting signals through differential mic inputs (micn, micp). moreover, an external resistor can be applied to adjust microphone gain and time of agc operating. the ad needs to select source of line-in before conversion. the adc take pad(avdd) as voltage reference. 6.13. spi a serial peripheral interface (spi) controller is built in GPCE048A to facilitate communicating with other devices and components. there are four control signals on spi - spics (ioa12), spick (ioa13), sdo (ioa14), and sdi (ioa15). 6.14. audio algorithm the following speech types can be used in GPCE048A: pcm, sacm_s200, sacm_s480, sacm_s530, sacm_s720, sacm_a1600, sacm_a1601, sacm_a3600, sacm_dvr520, sacm_dvr1600, sacm_dvr3200, and sacm_dvr4800. for melody synthesis, the GPCE048A supports sacm_ms01 (fm) and sacm_ms02 (wave-table) synthesizers.
GPCE048A ? generalplus technology inc. proprietary & confidential 13 oct. 04, 2013 version: 1.3 7. electrical specifications 7.1. absolute maximum ratings characteristics symbol ratings dc supply voltage v + < 4.0v porta/b pad supply voltage v io < 7.0v input voltage range v in -0.5v to v + + 0.5v operating temperature t a 0 to +60 storage temperature t sto -50 to +150 note: stresses beyond those given in the absolute maximum rating ta ble may cause operational errors or damage to the device. for no rmal operational conditions see dc electrical characteristics. 7.2. dc characteristics (vdd_reg = 3.3v, vddio = 4.5v (porta & b), t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd_reg 2.4 - 5.5 v - operating current i op - 18 - ma f osc = 49.152mhz, ad, dac disable, no load 4 a disable 32khz crystal standby current i stb b - - 9 a enable 32khz,disable pll(f osc ) input high level v ih 0.7vdd io - - v - input low level v il - - 0.3vdd io v - output dac current i aud - -4.8 - ma for one channel dac output high current i oh - -11 - ma v oh = 0.9vddio output low current (pa[3:0], pb[7:0]) i ol - 11 - ma v ol = 0.1vddio output low current (pa[7:4]) i ol - 25 - ma - input pull-low resister (pa15 :0, pb15 :8) r pl - 120 - k v in = vddio input pull-low resister (pb[7:0]) r pl - 1000 - k v in = vddio input pull-high resister (pa15 :0, pb15 :0) r ph - 110 - k v in = vss 7.3. dc characteristics (vdd_reg = 3.3v, vddio = 3.3v (porta & b), t a = 25 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd_reg 2.4 - 5.5 v - operating current i op - 17 - ma f osc = 49.152mhz, ad, dac disable, no load 3 a disable 32khz crystal standby current i stb b - - 6 a enable 32khz,disable pll(f osc ) input high level v ih 0.7vdd io - - v - input low level v il - - 0.3vdd io v - output dac current i aud - -3.5 - ma for one channel dac output high current i oh - -7 - ma v oh = 0.9vddio
GPCE048A ? generalplus technology inc. proprietary & confidential 14 oct. 04, 2013 version: 1.3 limit characteristics symbol min. typ. max. unit test condition output low current (pa[3:0], pb[7:0]) i ol - 6 - ma v ol = 0.1vddio output low current (pa[7:4]) i ol - 15 - ma - input pull-low resister (pa15 :0, pb15 :8) r pl - 180 - k v in = vddio input pull-low resister (pb[7:0]) r pl - 1400 - k v in = vddio input pull-high resister (pa15 :0, pb15 :0) r ph - 160 - k v in = vss 7.4. adc characteristics (avdd = 3.3v, t a = 25 ) limit characteristics symbol min. typ. max. unit adc line_in input voltage range from iob[7:0] vinl (note 1) vss-0.3 - avdd+0.3 v adc microphone input voltage range vinm vss-0.3 - avdd+0.3 v resolution of adc reso - - 12 bits signal-to-noise plus dist ortion of adc from line in sinad (note 3) - 60 - db effective number of bit enob (note 4) 8.0 9.0 - bits integral non-linearity of adc inl - 3.0 - lsb (note 2) differential non-linearity of adc dnl (note 6) - 1 - lsb ad conversion rate f conv - - f cpu /256 hz microphone amplifier gain a mic - - 42 db note1: internal protection diodes clamp the analog input to avdd and vss. these diodes allow the analog input to swing from (vss-0.3v ) to (avdd+0.3v) without causing damage to the devices. note2: lsb means least significant bit. with vinl = 2.6v, 1lsb = 2.6v/2^12 = 0.635mv. note3: the sinad testing condition at vinlp-p = 0.8*avdd, f conv = fcpu/512 = 49mhz/256 = 192khz , fin=1.0khz sine waves at avdd = 3.0v from the iob [7:0] input. note4: enob = (sinad-1.76)/6.02. note5: the adc of GPCE048A can guarantee 12 bits no missing code. note6: the microphone amplifier maximum gain = 15 * (60k/(1.5k+rext) v/ v. the rext is external resistor between opi and micout. the g ain is 132v/v (=42db) when rext is 5.1k. 7.5. dac characteristics (avdd = 3.3v, t a = 25 ) limit characteristics symbol min. typ. max. unit resolution of dac reso - - 14 bit signal to noise ratio of dac snr - 82 - db sample rate f s - - 400k hz thd+n at fs f out = 1k hz - 0.2 - %
GPCE048A ? generalplus technology inc. proprietary & confidential 15 oct. 04, 2013 version: 1.3 7.6. regulator characteristics ( t a = 25 ) unit characteristics symbol min. typ. max. unit input voltage vregi 2.4 5.5 v maximum current output irego - - 60 ma output voltage vrego 3.14 3.3 3.46 v standby current irges - 2.5 - ua 7.7. pull high resister and vddio rph vs vddio 0 50 100 150 200 250 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vddio (v) rph (kohm) 7.8. pull low resister and vddio(normal pad) rpl vs vddio (normal pad) 0 50 100 150 200 250 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vddio (v) rpl (kohm) 7.9. pull low resister and vddio(iob[7:0] pad with input high) rpl vs vddio (high resister pad) 0 500 1000 1500 2000 2500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vddio (v) rpl (kohm) 7.10. i/o output high current i oh and vddio output high current vs vddio 0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vddio (v) current (ma)
GPCE048A ? generalplus technology inc. proprietary & confidential 16 oct. 04, 2013 version: 1.3 7.11. i/o output low current i ol and vddio(normal pad) output low current vs vddio -16 -14 -12 -10 -8 -6 -4 -2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vddio (v) current (ma) 7.12. i/o output low current i ol and vddio(high driving pad) output low current vs vddio(high driving ioa[7:4]) -35 -30 -25 -20 -15 -10 -5 0 2.02.53.03.54.04.55.05.56. vddio (v) current (ma) 7.13. dac output current iol and avdd dac current vs vdd 0 1 2 3 4 5 6 7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) current (ma) 0
GPCE048A ? generalplus technology inc. proprietary & confidential 17 oct. 04, 2013 version: 1.3 8. application circuits 8.1. application circuit-(1) 8.1.1. application circuit (1) with regulator resetb dac ioa[15:0] ioa[15:0] iob[15:0] iob[15:0] 0.1uf vmic micp micn agc 0.1uf vadref opi micout x32i x32o 32768 hz 20 pf* vcoin 3.3k 3300pf 0.1uf 20 pf* vddh(2.4v~5.5v) battery 10uf 470k 3k 0.22uf 0.22uf 3k 1k mic 4.7uf 5.1k 0.22uf 5000pf speaker 0.1uf 1k 270 0.027uf 0.1uf 10k 100uf 0.1uf 0.1uf 10uf vdd_reg vss_reg vdd vss vddh (2.4v~5.5v) battery 0.1uf 10uf vdd33_reg vdd(3.3v) 0.1uf 10uf avdd avss vddiob vddioa vssiob vssioa GPCE048A application circuit ( mic_ in and gpy 0030aaudio amplifier ) resetb note*: these capacitor values are for design guidance only. the recomme nded 32k xtal features are esr=1 1.2~35k and cl1=cl2 =20~30pf ( including pcb parasitic loading, for example, user should apply additional 14~24pf on x32i and x32o if pcb parasitic loading is 6pf) note: vdd33_reg is output of built-in regulator with maximum current 60 ma. it is recommended that only use it for internal power pa d.
GPCE048A ? generalplus technology inc. proprietary & confidential 18 oct. 04, 2013 version: 1.3 8.1.2. application circui t (1) without regulator note*: these capacitor values are for design guidance only. the recomm ended 32k xtal features are esr=1 1.2~35k and cl1=cl2 =20~30pf ( including pcb parasitic loading, for example, user should apply additional 14~24pf on x32i and x32o if pcb parasitic loading is 6pf)
GPCE048A ? generalplus technology inc. proprietary & confidential 19 oct. 04, 2013 version: 1.3 8.2. application circuit-(2) 8.2.1. application circuit-(2) with regulator note*: these capacitor values are for design guidance only. the recommend ed 32k xtal features are esr=11.2~35k and cl1=cl2 =20~30pf ( including pcb parasitic loading, for example, user should apply additional 14~24pf on x32i and x32o if pcb parasitic loading is 6pf) note: vdd33_reg is output of built-in regulator with maximum current 60 ma. it is recommended that only use it for internal power pa d.
GPCE048A ? generalplus technology inc. proprietary & confidential 20 oct. 04, 2013 version: 1.3 8.2.2. application circuit-(2) without regulator resetb speaker dac ioa[15:0] ioa[15:0] iob[15:0] iob[15:0] 0.1uf vmic micp micn agc 0.1uf vadref opi micout x32i x32o 32768hz 20pf* vcoin 3.3k 3300pf 0.1uf 20pf* 4.7uf 2k 5000pf 1k vddh(2.4v~5.5v) battery 10uf 470k 3k 0.22uf 0.22uf 3k 1k mic 4.7uf 5.1k 0.22uf 5000pf GPCE048A GPCE048A application circuit(mic_in and with bjt amplifier) resetb vdd_reg vss_reg vdd vss vddh(2.4v~5.5v) battery 2.2uf vdd33_reg 0.1uf 10uf avdd avss vddiob vddioa vssiob vssioa vddh(2.4v~3.6v) battery 0.1uf 10uf note*: these capacitor values are for design guidance only. the recomm ended 32k xtal features are esr=1 1.2~35k and cl1=cl2 =20~30pf ( including pcb parasitic loading, for example, user should apply additional 14~24pf on x32i and x32o if pcb parasitic loading is 6pf)
GPCE048A ? generalplus technology inc. proprietary & confidential 21 oct. 04, 2013 version: 1.3 8.3. application circuit-(3) 8.3.1. application circuit-(3) with regulator resetb speaker dac ioa[15:0] ioa[15:0] iob[15:0] iob[15:0] 0.1uf vmic micp micn agc 0.1uf vadref opi micout x32i x32o 32768hz 20pf* vcoin 3.3k 3300pf 0.1uf 20pf* 4.7uf 2k 5000pf 1k iob[7:0] iob[7:0] ( 8- channel line in ) vddh (2.4v~5.5v) battery GPCE048A GPCE048A application circuit ( line_in and with bjt amplifier) resetb 0.1uf 10uf vdd_ reg vss_ reg vdd vss vddh (2 . 4v~5.5v) battery 0.1uf 10uf vdd33_ reg vdd(3.3v) 0.1uf 10uf avdd avss vddiob vddioa vssiob vssioa note*: these capacitor values are for design guidance only. the recomm ended 32k xtal features are esr=1 1.2~35k and cl1=cl2 =20~30pf ( including pcb parasitic loading, for example, user should apply additional 14~24pf on x32i and x32o if pcb parasitic loading is 6pf) note: vdd33_reg is output of built-in regulator with maximum current 60 ma. it is recommended that only use it for internal power pa d.
GPCE048A ? generalplus technology inc. proprietary & confidential 22 oct. 04, 2013 version: 1.3 8.3.2. application circ uit-(3) without regulator note*: these capacitor values are for design guidance only. the recomm ended 32k xtal features are esr=1 1.2~35k and cl1=cl2 =20~30pf ( including pcb parasitic loading, for example, user should apply additional 14~24pf on x32i and x32o if pcb parasitic loading is 6pf)
GPCE048A ? generalplus technology inc. proprietary & confidential 23 oct. 04, 2013 version: 1.3 9. package/pad locations 9.1. ordering information product number package type GPCE048A-nnnv-c chip form GPCE048A-nnnv-ql02x halogen free package note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z). note3: package form number (x = 1 - 9, serial number). 9.2. package information lqfp 64 outline dimensions dimension in mm symbol min. typ. max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 c1 0.09 - 0.16 d 12.00 d1 10.00 e 12.00 e1 10.00 e 0.50 bsc.
GPCE048A ? generalplus technology inc. proprietary & confidential 24 oct. 04, 2013 version: 1.3 10. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and patent indem nification provis ions stipulated in the terms of sale only. generalplus makes no warranty, express, st atutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) fr om patent infringement. furthermore, generalplus makes no warranty of merchantability or fitness for any purpose. generalplus reserves the right to halt production or alter the specifications and prices at any ti me without notice. accordingly, the reader is cautioned to verify that the data s heets and other information in this publication are current before placing orders. products descr ibed herein are intended for use in normal co mmercial applications. applications involving unusual environmental or reliability requirement s, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by generalplus for such applications. please note th at application circuits illustrated in this document are for reference purposes only.
GPCE048A ? generalplus technology inc. proprietary & confidential 25 oct. 04, 2013 version: 1.3 11. revision history date revision # description page oct. 04, 2013 1.3 1. add comair logo to the cover page 2. update x32k crystal's capaci tance note in application circuit oct. 13, 2010 1.2 modify 3. features. 4 dec. 28, 2009 1.1 1. modify section 6.9.1 i/o pwm. 2. modify section 6.12 adc (anal og to digital converter) / dac. 3. add application circuits to section 8. 12 13 19,21,23 mar. 16, 2009 1.0 released edition dec. 18, 2008 0.2 modify the package information in section 9.2. 18 nov. 11, 2008 0.1 original 20

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